The invention relates to a memory cell configuration and a method for fabricating it.
Such a method is disclosed for example in the reference by S. Nakamura, xe2x80x9cGiga-bit DRAM Cells With Low Capacitance and Low Resistance Bit-Lines on Buried MOSFETs and Capacitors by Using Bonded SOI Technologyxe2x80x94Reversed-Stacked-Capacitor (RSTC) Cellxe2x80x94xe2x80x9d IEDM 95, 889. The memory cell configuration produced by the method is a DRAM cell configuration, in other words a dynamic random access memory cell configuration. A memory cell of the memory cell configuration contains a transistor and a capacitor on which the information of the memory cell is stored in the form of a charge. The capacitor is connected to the transistor in such a way that when the transistor is driven via a word line, the charge of the capacitor can be read out via a bit line. The planar transistor and, above it, the capacitor are produced on a first surface of a substrate. Borophosphorus silicate glass (BPSG) is deposited over the capacitor and polished to produce a planar area. On this area, the substrate is connected to a support substrate. Afterward, a second surface of the substrate, the surface being opposite to the first surface, is removed until an insulating structure that surrounds the transistor is uncovered. After a thermal oxidation, an insulating material is deposited. In the insulating material, a contact hole to a source/drain region of the transistor is produced. A bit line is produced on the insulating material. Part of the bit line is disposed in the contact hole and adjoins the source/drain region.
It is accordingly an object of the invention to provide a memory cell configuration and a method for fabricating it that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which can be fabricated with an increased process reliability compared with the prior art.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration. The memory cell contains a substrate having a first surface and a second surface disposed opposite to the first surface, a bit line, and a metal oxide semiconductor transistor connected to the bit line and disposed on the first surface. A capacitor is disposed on the second surface of the substrate, and a contact is disposed in the substrate and connects the capacitor to the MOS transistor.
The problem is solved by the memory cell configuration in which the metal oxide semiconductor (MOS) transistor of the memory cell and the bit line connected thereto are disposed on the first surface of the substrate. The capacitor of the memory cell is disposed on the second surface of the substrate, the surface being opposite to the first surface. A contact disposed in the substrate connects the capacitor to the MOS transistor.
The problem is furthermore solved by a method for fabricating a memory cell configuration in which a MOS transistor of a memory cell and a bit line connected thereto are produced on a first surface of a substrate. A second surface of the substrate, the surface being opposite to the first surface, is removed. A capacitor of the memory cell is produced on the second surface. A contact that connects the capacitor to the MOS transistor is produced in the substrate.
The influence of the method for producing the capacitor on the MOS transistor is slight because the MOS transistor is disposed on a different side of the substrate than the capacitor. The invention consequently enables many degrees of freedom for the production of the capacitors, for example with regard to the choice of materials and also the choice of process steps. The process reliability is increased compared with the prior art.
In order to increase the packing density of the memory cell configuration, it is advantageous to produce the contact in the first surface in such a way that it reaches more deeply into the substrate than the MOS transistor and the bit line, subsequently to remove the second surface of the substrate until the contact is uncovered, and finally, on the second surface, to produce the capacitor on the contact.
As a result of the contact being uncovered, its position is identified, so that the capacitor can be exactly aligned with respect to the MOS transistor. The memory cell configuration can consequently be produced with a high packing density.
In order to increase a capacitance of the capacitor, a surface of a capacitor electrode on which a capacitor dielectric is disposed, is as large as possible. To ensure that a packing density of the DRAM cell configuration is as large as possible, a space requirement of the capacitor is as small as possible. Both advantages can be obtained if the surface of the capacitor electrode has protuberances and/or indentations.
In order to increase the capacitance of the capacitor, the capacitor dielectric preferably has a dielectric constant of more than 20. By way of example, the capacitor dielectric is composed of a ferroelectric, such as e.g. barium strontium titanate or of Ta2O5.
The contact connects a first source/drain region of the MOS transistor to the capacitor electrode of the capacitor. A second source/drain region of the MOS transistor is connected to the bit line. A gate electrode of the MOS transistor is connected to a word line that runs transversely with respect to the bit line. The bit line may, for example, run above the first surface of the substrate.
The MOS transistor may be configured as a planar transistor.
In order to increase the packing density of the memory cell configuration, the MOS transistor is preferably produced as a vertical transistor. The first source/drain region is disposed below the second source/drain region, for example. The first source/drain region can laterally adjoin the contact.
It lies within the scope of the invention to produce the first source/drain region above the second source/drain region.
A contact hole is preferably produced in the first surface. In order to produce the contact, a conductive material is deposited and etched back in such a way that the contact hole is not completely filled. The depth of an upper surface of the contact is dimensioned in such a way that the contact adjoins the first source/drain region, which may be part of the substrate and is disposed below the second source/drain region. Before the production of the contact, the contact hole is provided with an insulation, with the result that the contact is insulated from the rest of the substrate. In the contact hole, a gate electrode of the MOS transistor is produced above the contact, the gate electrode being insulated from the contact and substrate. The second source/drain region is likewise produced as part of the substrate and laterally adjoins the contact hole.
As an alternative, the gate electrode is produced in a substrate depression that is different from the contact hole.
The contact preferably protrudes from the second surface of the substrate. In this case, a short circuit between the substrate and the contact when producing the capacitor electrode can be avoided particularly easily by insulating material being deposited and removed until the contact is uncovered. The substrate is then covered with the insulating material, and the capacitor electrode can be produced on the insulating material and on the contact, without it adjoining the substrate.
One possibility for being able to achieve the result that the capacitor protrudes from the second surface of the substrate is described below. After the substrate is removed until the contact is uncovered, the contact is etched selectively with respect to the substrate, a depression thereby being produced. The depression is filled with an auxiliary structure, with the result that the auxiliary structure covers the contact. For this purpose, material is deposited and removed until the substrate is uncovered. Afterward, the substrate is etched selectively with respect to the auxiliary structure, with the result that the auxiliary structure and also part of the contact protrude. The insulating material can then be deposited and removed together with the auxiliary structure until the auxiliary structure is removed and, consequently, the contact is uncovered. The insulating material and a surface of the contact form a planar area. At the same time, the contact protrudes beyond the second surface of the substrate.
The substrate may be composed of silicon. The contact may be composed of doped polysilicon. An example of a suitable etchant for selectively etching the contact is a solution containing HF, HNO3 and CH3COOH.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration and a method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.